Grant and Recordal of Patent: Pass Transistor Adiabatic Circuit with Stand-By Mode (PAL2NSM) Logic Style
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MOU being signed between Dr. Vishwanath Karad MIT World Peace University #MIT-WPU and #ARAI, #Pune for research collaboration on July 4, 2020
https://www.linkedin.com/posts/engineering-mitwpu_mou-mit-arai-activity-6687258374339387392-9pgo
I am pleased to share with you that Semiconductor Laboratory, Department of Space has issued the certificate of successful fabrication and testing of my IC. To the best of my knowledge, a handful researcher working in private Indian universities might have fabricated their own designs on silicon. This fabrication costs around 15-30L depending upon technology but SCL did it free for me.
Optimal Conditions for Ultra Low Power Digital Circuits
Increasing demands to improve VLSI digital system performance fueled the necessity of low-power design methodology. Historically, the system performance had been synonymous with circuit speed and processing power. But recently, area and time are not the only parameters to be considered while deciding the system performance. Power consumption is yet another metric. Adiabatic logic, which works on the principle of Energy Recovery, is proving to be an emerging low power approach in low power design. This paper will help in selecting the maximum frequency, device size and the fan-out to design 2:1 multiplexer circuit for ultra-low power application. The outcome of this research work will provide guidelines for designing ultra-low power circuits using adiabatic technique. All the circuits are designed using cell based design approach and 180 μm device size in Cadence. Keywords: Adiabatic, Energy-Recovery, PAL, CAL
How Higher Education will Change Post Pandemic in India
https://www.youtube.com/watch?v=jwcUh6utWWk&feature=youtu.be
